1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of using ion implantations to form interface layer in a gate structure.
2. Description of the Prior Art
In current semiconductor industry, polysilicon has been widely used as a gap-filling material for fabricating gate electrode of metal-oxide-semiconductor (MOS) transistors. However, the conventional polysilicon gate also faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of gate dielectric layer, reduces gate capacitance, and worsens driving force of the devices. In replacing polysilicon gates, work function metals have been developed to serve as a control electrode working in conjunction with high-K gate dielectric layers.
Nevertheless, as semiconductor technology advances, gate structures employing work function materials soon reaches their physical and electrical limitation, causing side-effects including electrical instability and negative bias temperature instability (NBTI) effect.
NBTI effect is typically caused by accumulation of electrical potentials between silicon substrate and silicon oxide layers, which induces an effect when gate electrode is negatively biased. As PMOS transistors apply negative bias to generate electrons on metal gate adjacent to gate oxide, reject electrons on n-type substrate, and generate electron holes on n-type substrate and electron hole channel under gate structure thereby inducing electron holes of the source/drain region to be transmitted through this channel, NBTI effect is especially influential in CMOS devices containing PMOS structures.